ਇੰਟਲ ਪ੍ਰੋਸੈਸਰਾਂ ਦੀ ਸੂਚੀ
4-ਬਿੱਟ ਪ੍ਰੋਸੈਸਰ
ਸੋਧੋFirst microprocessor (single-chip IC processor)
- Clock rate 740 kHz[1]
- 0.07 MIPS
- Bus width 4 bits (multiplexed address/data due to limited pins)
- PMOS
- Number of transistors 2,300 at 10μm
- Addressable Memory 640bytes
- Program Memory 4KB
- One of the earliest Commercial Microprocessors (cf. Four Phase Systems AL1, F14 CADC)
- Originally designed to be used in Busicom calculator
MCS-4 Family:
- 4004 – CPU
- 4001 – ROM & 4-bit Port
- 4002 – RAM & 4-bit Port
- 4003 – 10-bit Shift Register
- 4008 – Memory+I/O Interface
- 4009 – Memory+I/O Interface
- Introduced November 15 1971
MCS-40 Family:
- 4040 – CPU
- 4101 – 1024-bits (256 × 4) Static RAM with separate I/O
- 4201 – 4 MHz Clock Generator
- 4207 – General Purpose Byte I/O Port
- 4209 – General Purpose Byte I/O Port
- 4211 – General Purpose Byte I/O Port
- 4265 – Programmable General Purpose I/O Device
- 4269 – Programmable Keyboard Display Device
- 4289 – Standard Memory Interface for MCS-4/40
- 4308 – 8192-bit (1024 × 8) ROM w/ 4-bit I/O Ports
- 4316 – 16384-bit (2048 × 8) Static ROM
- 4702 – 2048-bit (256 × 8) EPROM
- 4801 – 5.185 MHz Clock Generator Crystal for 4004/4201A or 4040/4201A
- Introduced 1971
- Introduced April 1, 1972
- Clock rate 500 kHz (8008–1: 800 kHz)
- 0.05 MIPS
- Bus width 8 bits (multiplexed address/data due to limited pins)
- Enhancement load PMOS logic
- Number of transistors 3,500 at 10μm
- Addressable memory 16 KB
- Typical in early 8-bit microcomputers, dumb terminals, general calculators, bottling machines
- Developed in tandem with 4004
- Originally intended for use in the Datapoint 2200 microcomputer
- Key volume deployment in Texas Instruments 742 microcomputer in >3,000 Ford dealerships
- Introduced April 1, 1974
- Clock rate 2 MHz (very rare 8080B: 3 MHz)
- 0.29 MIPS[2]
- Bus width 8 bits data, 16 bits address
- Enhancement load NMOS logic
- Number of transistors 4,500, 6μm
- Assembly language downwards compatible with 8008.
- Addressable memory 64 KB
- Up to 10X the performance of the 8008
- Used in the Altair 8800, Traffic light controller, cruise missile
- Required six support chips versus 20 for the 8008
- Introduced March 1976
- Clock rate 3 MHz[3]
- 0.37 MIPS
- Bus width 8 bits data, 16 bits address
- Depletion load NMOS logic
- Number of transistors 6,500 at 3μm
- Binary compatible downwards with the 8080.
- Used in Toledo scales. Also was used as a computer peripheral controller – modems, hard disks, printers, etc.
- CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable.
Microcontrollers
ਸੋਧੋThey are ICs with CPU, RAM, ROM (or PROM or EPROM), I/O Ports, Timers & Interrupts
- Single accumulator Harvard architecture
MCS-48 family:
- 8020 – Single-Component 8-bit Microcontroller
- 8021 – Single-Component 8-bit Microcontroller
- 8022 – Single-Component 8-bit Microcontroller With On-Chip A/D Converter
- 8035 – Single-Component 8-bit Microcontroller
- 8039 – Single-Component 8-bit Microcontroller
- 8040 – Single-Component 8-bit Microcontroller
- 8041 – Universal Peripheral Interface 8-bit Slave Microcontroller
- 8641 – Universal Peripheral Interface 8-bit Slave Microcontroller
- 8741 – Universal Peripheral Interface 8-bit Slave Microcontroller
- 8042 – Universal Peripheral Interface 8-bit Slave Microcontroller
- 8742 – Universal Peripheral Interface 8-bit Slave Microcontroller
- 8243 – Input/Output Expander
- 8244 – custom (NTSC)
- 8245 – custom (PAL)
- 8048 – Single-Component 8-bit Microcontroller
- 8048 – Single-Component 8-bit Microcontroller
- 8748 – Single-Component 8-bit Microcontroller
- 8048 – Single-Component 8-bit Microcontroller
- 8049 – Single-Component 8-bit Microcontroller
- 8749 – Single-Component 8-bit Microcontroller
- 8050 – Single-Component 8-bit Microcontroller
- Single accumulator Harvard architecture
MCS-51 Family:
- 8031 – 8-bit Control-Oriented Microcontroller
- 8032 – 8-bit Control-Oriented Microcontroller
- 8044 – High Performance 8-bit Microcontroller
- 8344 – High Performance 8-bit Microcontroller
- 8744 – High Performance 8-bit Microcontroller
- 8051 – 8-bit Control-Oriented Microcontroller
- 8052 – 8-bit Control-Oriented Microcontroller
- 8054 – 8-bit Control-Oriented Microcontroller
- 8058 – 8-bit Control-Oriented Microcontroller
- 8351 – 8-bit Control-Oriented Microcontroller
- 8352 – 8-bit Control-Oriented Microcontroller
- 8354 – 8-bit Control-Oriented Microcontroller
- 8358 – 8-bit Control-Oriented Microcontroller
- 8751 – 8-bit Control-Oriented Microcontroller
- 8752 – 8-bit Control-Oriented Microcontroller
- 8754 – 8-bit Control-Oriented Microcontroller
- 8758 – 8-bit Control-Oriented Microcontroller
- Single accumulator Harvard architecture
MCS-151 Family:
- 80151 – High Performance 8-bit Control-Oriented Microcontroller
- 83151 – High Performance 8-bit Control-Oriented Microcontroller
- 87151 – High Performance 8-bit Control-Oriented Microcontroller
- 80152 – High Performance 8-bit Control-Oriented Microcontroller
- 83152 – High Performance 8-bit Control-Oriented Microcontroller
- Single accumulator Harvard architecture
MCS-251 Family:
- 80251 – 8/16/32-bit Microcontroller
- 80252 – 8/16/32-bit Microcontroller
- 80452 – 8/16/32-bit Microcontroller
- 83251 – 8/16/32-bit Microcontroller
- 87251 – 8/16/32-bit Microcontroller
- 87253 – 8/16/32-bit Microcontroller
- 8094 – 16-bit Microcontroller (48-Pin ROMLess Without A/D)
- 8095 – 16-bit Microcontroller (48-Pin ROMLess With A/D)
- 8096 – 16-bit Microcontroller (68-Pin ROMLess Without A/D)
- 8097 – 16-bit Microcontroller (68-Pin ROMLess With A/D)
- 8394 – 16-bit Microcontroller (48-Pin With ROM Without A/D)
- 8395 – 16-bit Microcontroller (48-Pin With ROM With A/D)
- 8396 – 16-bit Microcontroller (68-Pin With ROM Without A/D)
- 8397 – 16-bit Microcontroller (68-Pin With ROM With A/D)
- 8794 – 16-bit Microcontroller (48-Pin With EROM Without A/D)
- 8795 – 16-bit Microcontroller (48-Pin With EROM With A/D)
- 8796 – 16-bit Microcontroller (68-Pin With EROM Without A/D)
- 8797 – 16-bit Microcontroller (68-Pin With EROM With A/D)
- 8098 – 16-bit Microcontroller
- 8398 – 16-bit Microcontroller
- 8798 – 16-bit Microcontroller
- 80196 – 16-bit Microcontroller
- 83196 – 16-bit Microcontroller
- 87196 – 16-bit Microcontroller
- 80296 – 16-bit Microcontroller
3000 Family
ਸੋਧੋ
Introduced in the third quarter of 1974, these components used bipolar Schottky transistors. Each component implemented two bits of a processor function; packages could be interconnected to build a processor with any desired word length. Members of the family:
- 3001 – Microcontrol Unit
- 3002 – 2-bit Arithmetic Logic Unit slice
- 3003 – Look-ahead Carry Generator
- 3205 – High-performance 1 Of 8 Binary Decoder
- 3207 – Quad Bipolar-to-MOS Level Shifter and Driver
- 3208 – Hex Sense Amp and Latch for MOS Memories
- 3210 – TTL-to-MOS Level Shifter and High Voltage Clock Driver
- 3211 – ECL-to-MOS Level Shifter and High Voltage Clock Driver
- 3212 – Multimode Latch Buffer
- 3214 – Interrupt Control Unit
- 3216 – Parallel, Inverting Bi-Directional Bus Driver
- 3222 – Refresh Controller for 4K NMOS DRAMs
- 3226 – Parallel, Inverting Bi-Directional Bus Driver
- 3232 – Address Multiplexer and Refresh Counter for 4K DRAMs
- 3242 – Address Multiplexer and Refresh Counter for 16K DRAMs
- 3245 – Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K
- 3246 – Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K
- 3404 – High-performance 6-bit Latch
- 3408 – Hex Sense Amp and Latch for MOS Memories
- 3505 - Next generation processor
Bus width 2*n bits data/address (depending on number n of slices used)
- Introduced June 8, 1978
- Clock rates:
- 5 MHz with 0.33 MIPS[3]
- 8 MHz with 0.66 MIPS
- 10 MHz with 0.75 MIPS
- The memory is divided into odd and even banks; it accesses both banks concurrently to read 16 bits of data in one clock cycle
- Bus width 16 bits data, 20 bits address
- Number of transistors 29,000 at 3μm
- Addressable memory 1megabyte
- Up to 10X the performance of 8080
- First used in the Compaq Deskpro IBM PC-compatible computers. Later used in portable computing, and in the IBM PS/2 Model 25 and Model 30. Also used in the AT&T PC6300 / Olivetti M24, a popular IBM PC-compatible (predating the IBM PS/2 line).
- Used segment registers to access more than 64 KB of data at once, which many programmers complained made their work excessively difficult.[ਹਵਾਲਾ ਲੋੜੀਂਦਾ]
- The first x86 CPU.
- Later renamed the iAPX 86[4]
- Introduced June 1, 1979
- Clock rates:
- 4.77 MHz with 0.33 MIPS
- 8 MHz with 0.66 MIPS[3]
- Internal architecture 16 bits
- External bus Width 8 bits data, 20 bits address
- Number of transistors 29,000 at 3μm
- Addressable memory 1megabyte
- Identical to 8086 except for its 8-bit external bus (hence an 8 instead of a 6 at the end); identical Execution Unit (EU), different Bus Interface Unit (BIU)[4]
- Used in IBM PC and PC-XT and compatibles
- Later renamed the iAPX 88[4]
- Introduced 1982
- Clock rates
- 6 MHz with > 1 MIPS
- Number of transistors 55000
- Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor (these were at fixed addresses which differed from the IBM PC, although it was used by several PC compatible vendors such as Australian company Cleveland).
- Added a few opcodes and exceptions to the 8086 design; otherwise identical instruction set to 8086 and 8088
- BOUND, ENTER, LEAVE
- INS, OUTS
- IMUL imm, PUSH imm, PUSHA, POPA
- RCL/RCR/ROL/ROR/SHL/SHR/SAL/SAR reg,imm
- Address calculation and shift operations are faster than 8086
- Used mostly in embedded applications – controllers, point-of-sale systems, terminals, and the like
- Used in several non-PC compatible DOS computers including RM Nimbus, Tandy 2000, and CP/M 86 Televideo PM16 server
- Later renamed to iAPX 186
- A version of the 80186 with an 8-bit external data bus
- Later renamed the iAPX 188
- Introduced February 2, 1982
- Clock rates:
- 6 MHz with 0.9 MIPS
- 8 MHz, 10 MHz with 1.5 MIPS
- 12.5 MHz with 2.66 MIPS
- 16 MHz, 20 MHz and 25 MHz available.
- Bus width: 16 bits data, 24 bits address.
- Included memory protection hardware to support multitasking operating systems with per-process address space.
- Number of transistors 134,000 at 1.5μm
- Addressable memory 16MB
- Added protected-mode features to 8086 with essentially the same instruction set
- 3–6X the performance of the 8086
- Widely used in IBM-PC AT and AT clones contemporary to it.
- Introduced January 1, 1981 as ਇੰਟਲ's first 32-bit microprocessor
- Multi-chip CPU; ਇੰਟਲ's first 32-bit microprocessor
- Object/capability architecture
- Microcoded operating system primitives
- One terabyte virtual address space
- Hardware support for fault tolerance
- Two-chip General Data Processor (GDP), consists of 43201 and 43202
- 43203 Interface Processor (IP) interfaces to I/O subsystem
- 43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
- 43205 Memory Control Unit (MCU)
- Architecture and execution unit internal data base paths 32 bit
- Clock rates:
- 5 MHz
- 7 MHz
- 8 MHz
- Introduced April 5, 1988
- RISC-like 32-bit architecture
- Predominantly used in embedded systems
- Evolved from the capability processor developed for the BiiN joint venture with Siemens
- Many variants identified by two-letter suffixes.
- Introduced February 26, 1989
- RISC 32/64-bit architecture, with floating point pipeline characteristics very visible to programmer
- Used in the ਇੰਟਲ iPSC/860 Hypercube parallel supercomputer
- Mid-life kicker in the i870 processor (primarily a speed bump, some refinement/extension of instruction set)
- Used in the ਇੰਟਲ Delta massively parallel supercomputer prototype, emplaced at California Institute of Technology
- Used in the ਇੰਟਲ Paragon massively parallel supercomputer, emplaced at Sandia National Laboratory
- Introduced August 23, 2000
- 32-bit RISC microprocessor based on the ARM architecture
- Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors.
- Introduced October 17, 1985
- Clock rates:
- 16 MHz with 5 MIPS
- 20 MHz with 6 to 7 MIPS, introduced February 16, 1987
- 25 MHz with 7.5 MIPS, introduced April 4, 1988
- 33 MHz with 9.9 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced April 10, 1989
- Bus width 32 bits data, 32 bits address
- Number of transistors 275,000 at 1μm
- Addressable memory 4GB
- Virtual memory 64 TB
- First x86 chip to handle 32-bit data sets
- Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required at the time by Xenix and Unix. This memory capability spurred the development and availability of OS/2 and is a fundamental requirement for modern operating systems like Linux, Windows, and OS X.
- First used by Compaq in the Deskpro 386. Used in desktop computing
- Unlike the DX naming convention of the 486 chips, it had no math co-processor.
- Later renamed ਇੰਟਲ386 DX
- Introduced June 16, 1988
- Clock rates:
- 16 MHz with 2.5 MIPS
- 20 MHz with 3.1 MIPS, introduced January 25, 1989
- 25 MHz with 3.9 MIPS, introduced January 25, 1989
- 33 MHz with 5.1 MIPS, introduced October 26, 1992
- Internal architecture 32 bits
- External data bus width 16 bits
- External address bus width 24 bits
- Number of transistors 275,000 at 1μm
- Addressable memory 16MB
- Virtual memory 32GB
- Narrower buses enable low-cost 32-bit processing
- Used in entry-level desktop and portable computing
- No math co-processor
- No commercial software used for protected mode or virtual storage for many years
- Later renamed ਇੰਟਲ386 SX
- Introduced January 16, 1989; discontinued June 15, 2001
- Variant of 386SX intended for embedded systems
- No "real mode", starts up directly in "protected mode"
- Replaced by much more successful 80386EX from 1994
- Introduced October 15, 1990
- Clock rates:
- 20 MHz with 4.21 MIPS
- 25 MHz with 5.3 MIPS, introduced September 30, 1991
- Internal architecture 32 bits
- External bus width 16 bits
- Number of transistors 855,000 at 1μm
- Addressable memory 4GB
- Virtual memory 1 TB
- First chip specifically made for portable computers because of low power consumption of chip
- Highly integrated, includes cache, bus, and memory controllers
- Introduced August 1994
- Variant of 80386SX intended for embedded systems
- Static core, i.e. may run as slowly (and thus, power efficiently) as desired, down to full halt
- On-chip peripherals:
- Clock and power management
- Timers/counters
- Watchdog timer
- Serial I/O units (sync and async) and parallel I/O
- DMA
- RAM refresh
- JTAG test logic
- Significantly more successful than the 80376
- Used aboard several orbiting satellites and microsatellites
- Used in NASA's FlightLinux project
32-bit processors: the 80486 range
ਸੋਧੋ- Introduced April 10, 1989
- Clock rates:
- 25 MHz with 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
- 33 MHz with 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KB L2), introduced May 7, 1990
- 50 MHz with 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KB L2), introduced June 24, 1991
- Bus width 32 bits
- Number of transistors 1.2 million at 1μm; the 50 MHz was at 0.8μm
- Addressable memory 4GB
- Virtual memory 1 TB
- Level 1 cache of 8 KB on chip
- Math coprocessor on chip
- 50X performance of the 8088
- Officially named ਇੰਟਲ486 DX
- Used in Desktop computing and servers
- Family 4 model 1
- Introduced April 22, 1991
- Clock rates:
- 16 MHz with 13 MIPS
- 20 MHz with 16.5 MIPS, introduced September 16, 1991
- 25 MHz with 20 MIPS (12 SPECint92), introduced September 16, 1991
- 33 MHz with 27 MIPS (15.86 SPECint92), introduced September 21, 1992
- Bus width 32 bits
- Number of transistors 1.185 million at 1μm and 900,000 at 0.8μm
- Addressable memory 4GB
- Virtual memory 1 TB
- Identical in design to 486DX but without math coprocessor. The first version was an 80486DX with disabled math coprocessor in the chip and different pin configuration. If the user needed math coprocessor capabilities, he must add 487SX which was actually an 486DX with different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPU's with only 1 effectively turned on
- Officially named ਇੰਟਲ486 SX
- Used in low-cost entry to 486 CPU desktop computing, as well as extensively used in low cost mobile computing.
- Upgradable with the ਇੰਟਲ OverDrive processor
- Family 4 model 2
- Introduced March 3, 1992
Runs at twice the speed of the external bus (FSB). Fits on Socket 3
- Clock rates:
- 40 MHz
- 50 MHz
- 66 MHz
- Officially named ਇੰਟਲ486 DX2
- Family 4 model 3
- Introduced November 9, 1992
- Clock rates:
- 20 MHz with 15.4 MIPS
- 25 MHz with 19 MIPS
- 33 MHz with 25 MIPS
- Bus width 32 bits
- Number of transistors 1.4 million at 0.8μm
- Addressable memory 4GB
- Virtual memory 1 TB
- Officially named ਇੰਟਲ486 SL
- Used in notebook computers
- Family 4 model 4
- Introduced March 7, 1994
- Clock rates:
- 75 MHz with 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KB L2)
- 100 MHz with 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KB L2)
- Number of transistors 1.6 million at 0.6μm
- Bus width 32 bits
- Addressable memory 4GB
- Virtual memory 64 TB
- Pin count 168 PGA Package, 208 sq ftP Package
- Officially named ਇੰਟਲ486 DX4
- Used in high performance entry-level desktops and value notebooks
- Family 4 model 8
- Bus width 64 bits
- System bus clock rate 60 or 66 MHz
- Address bus 32 bits
- Addressable Memory 4GB
- Virtual Memory 1 TB
- Superscalar architecture
- Runs on 3.3 Volts (except the very first generation "P5")
- Used in desktops
- 8 KB of instruction cache
- 8 KB of data cache
- P5 – 0.8μm process technology
- Introduced March 22, 1993
- Number of transistors 3.1 million
- The only Pentium running on 5 Volts
- Socket 4 273 pin PGA processor package
- Package dimensions 2.16" × 2.16"
- Family 5 model 1
- Variants
- 60 MHz with 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256 KB L2)
- 66 MHz with 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256 KB L2)
- P54 – 0.6μm process technology
- Socket 5 296/320 pin PGA package
- Number of transistors 3.2 million
- Variants
- 75 MHz with 126.5 MIPS (2.31 SPECint95, 2.02 SPECfp95 on Gateway P5 256K L2)
- Introduced October 10, 1994
- 90, 100 MHz with 149.8 and 166.3 MIPS respectively (2.74 SPECint95, 2.39 SPECfp95 on Gateway P5 256K L2 and 3.30 SPECint95, 2.59 SPECfp95 on Xpress 1ML2 respectively)
- Introduced March 7, 1994
- 75 MHz with 126.5 MIPS (2.31 SPECint95, 2.02 SPECfp95 on Gateway P5 256K L2)
- P54CQS – 0.35μm process technology
- Socket 5 296/320 pin PGA package
- Number of transistors 3.2 million
- Variants
- 120 MHz with 203 MIPS (3.72 SPECint95, 2.81 SPECfp95 on Xpress 1MB L2)
- Introduced March 27, 1995
- 120 MHz with 203 MIPS (3.72 SPECint95, 2.81 SPECfp95 on Xpress 1MB L2)
- P54CS – 0.35μm process technology
- Number of transistors 3.3 million
- 90mm² die size
- Family 5 model 2
- Variants
- Socket 5 296/320 pin PGA package
- 133 MHz with 218.9 MIPS (4.14 SPECint95, 3.12 SPECfp95 on Xpress 1MB L2)
- Introduced June 12, 1995
- 150, 166 MHz with 230 and 247 MIPS respectively
- Introduced January 4, 1996
- 133 MHz with 218.9 MIPS (4.14 SPECint95, 3.12 SPECfp95 on Xpress 1MB L2)
- Socket 7 296/321 pin PGA package
- 200 MHz with 270 MIPS (5.47 SPECint95, 3.68 SPECfp95)
- Introduced June 10, 1996
- 200 MHz with 270 MIPS (5.47 SPECint95, 3.68 SPECfp95)
- P55C – 0.35μm process technology
- Introduced January 8, 1997
- ਇੰਟਲ MMX (instruction set) support
- Socket 7 296/321 pin PGA (pin grid array) package
- 16 KB L1 instruction cache
- 16 KB L1 data cache
- Number of transistors 4.5 million
- System bus clock rate 66 MHz
- Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8
- Variants
- 166, 200 MHz Introduced January 8, 1997
- 233 MHz Introduced June 2, 1997
- 133 MHz (Mobile)
- 166, 266 MHz (Mobile) Introduced January 12, 1998
- 200, 233 MHz (Mobile) Introduced September 8, 1997
- 300 MHz (Mobile) Introduced January 7, 1999
- Introduced November 1, 1995
- Precursor to Pentium II and III
- Primarily used in server systems
- Socket 8 processor package (387 pins) (Dual SPGA)
- Number of transistors 5.5 million
- Family 6 model 1
- 0.6μm process technology
- 16 KB L1 cache
- 256 KB integrated L2 cache
- 60 MHz system bus clock rate
- Variants
- 150 MHz
- 0.35μm process technology, or 0.35μm CPU with 0.6μm L2 cache
- Number of transistors 5.5 million
- 512 KB or 256 KB integrated L2 cache
- 60 or 66 MHz system bus clock rate
- Variants
- 166 MHz (66 MHz bus clock rate, 512 KB 0.35μm cache) Introduced November 1, 1995
- 180 MHz (60 MHz bus clock rate, 256 KB 0.6μm cache) Introduced November 1, 1995
- 200 MHz (66 MHz bus clock rate, 256 KB 0.6μm cache) Introduced November 1, 1995
- 200 MHz (66 MHz bus clock rate, 512 KB 0.35μm cache) Introduced November 1, 1995
- 200 MHz (66 MHz bus clock rate, 1MB 0.35μm cache) Introduced August 18, 1997
- Introduced May 7, 1997
- Pentium Pro with MMX and improved 16-bit performance
- 242-pin Slot 1 (SEC) processor package
- Voltage identification pins
- Number of transistors 7.5 million
- 32 KB L1 cache
- 512 KB 1⁄2 bandwidth external L2 cache
- The only Pentium II that did not have the L2 cache at 1⁄2 bandwidth of the core was the Pentium II 450 PE.
- Klamath – 0.35μm process technology (233, 266, 300 MHz)
- 66 MHz system bus clock rate
- Family 6 model 3
- Variants
- 233, 266, 300 MHz Introduced May 7, 1997
- Deschutes – 0.25μm process technology (333, 350, 400, 450 MHz)
- Introduced January 26, 1998
- 66 MHz system bus clock rate (333MHz variant), 100 MHz system bus clock rate for all models after
- Family 6 model 5
- Variants
- 333 MHz Introduced January 26, 1998
- 350, 400 MHz Introduced April 15, 1998
- 450 MHz Introduced August 24, 1998
- 233, 266 MHz (Mobile) Introduced April 2, 1998
- 333 MHz Pentium II Overdrive processor for Socket 8 Introduced August 10, 1998
- 300 MHz (Mobile) Introduced September 9, 1998
- 333 MHz (Mobile) Introduced January 25, 1999
- Covington – 0.25μm process technology
- Introduced April 15, 1998
- 242-pin Slot 1 SEPP (Single Edge Processor Package)
- Number of transistors 7.5 million
- 66 MHz system bus clock rate
- Slot 1
- 32 KB L1 cache
- No L2 cache
- Variants
- 266 MHz Introduced April 15, 1998
- 300 MHz Introduced June 9, 1998
- Mendocino – 0.25μm process technology
- Introduced August 24, 1998
- 242-pin Slot 1 SEPP (Single Edge Processor Package), Socket 370 PPGA package
- Number of transistors 19 million
- 66 MHz system bus clock rate
- Slot 1, Socket 370
- 32 KB L1 cache
- 128 KB integrated cache
- Family 6 model 6
- Variants
- 300, 333 MHz Introduced August 24, 1998
- 366, 400 MHz Introduced January 4, 1999
- 433 MHz Introduced March 22, 1999
- 466 MHz
- 500 MHz Introduced August 2, 1999
- 533 MHz Introduced January 4, 2000
- 266 MHz (Mobile)
- 300 MHz (Mobile)
- 333 MHz (Mobile) Introduced April 5, 1999
- 366 MHz (Mobile)
- 400 MHz (Mobile)
- 433 MHz (Mobile)
- 450 MHz (Mobile) Introduced February 14, 2000
- 466 MHz (Mobile)
- 500 MHz (Mobile) Introduced February 14, 2000
Pentium II Xeon (chronological entry)
- Introduced June 29, 1998
- See main entry
- Katmai – 0.25μm process technology
- Introduced February 26, 1999
- Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE)
- Number of transistors 9.5 million
- 512 KB 1⁄2 bandwidth L2 External cache
- 242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package
- System Bus clock rate 100 MHz, 133 MHz (B-models)
- Slot 1
- Family 6 model 7
- Variants
- 450, 500 MHz Introduced February 26, 1999
- 550 MHz Introduced May 17, 1999
- 600 MHz Introduced August 2, 1999
- 533, 600 MHz Introduced (133 MHz bus clock rate) September 27, 1999
- Coppermine – 0.18μm process technology
- Introduced October 25, 1999
- Number of transistors 28.1 million
- 256 KB Advanced Transfer L2 Cache (Integrated)
- 242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (Flip-chip pin grid array) package
- System Bus clock rate 100 MHz (E-models), 133 MHz (EB models)
- Slot 1, Socket 370
- Family 6 model 8
- Variants
- 500 MHz (100 MHz bus clock rate)
- 533 MHz
- 550 MHz (100 MHz bus clock rate)
- 600 MHz
- 600 MHz (100 MHz bus clock rate)
- 650 MHz (100 MHz bus clock rate) Introduced October 25, 1999
- 667 MHz Introduced October 25, 1999
- 700 MHz (100 MHz bus clock rate) Introduced October 25, 1999
- 733 MHz Introduced October 25, 1999
- 750, 800 MHz (100 MHz bus clock rate) Introduced December 20, 1999
- 850 MHz (100 MHz bus clock rate) Introduced March 20, 2000
- 866 MHz Introduced March 20, 2000
- 933 MHz Introduced May 24, 2000
- 1000 MHz Introduced March 8, 2000 (not widely available at time of release)
- 1100 MHz
- 1133 MHz (first version recalled, later re-released)
- 400, 450, 500 MHz (Mobile) Introduced October 25, 1999
- 600, 650 MHz (Mobile) Introduced January 18, 2000
- 700 MHz (Mobile) Introduced April 24, 2000
- 750 MHz (Mobile) Introduced June 19, 2000
- 800, 850 MHz (Mobile) Introduced September 25, 2000
- 900, 1000 MHz (Mobile) Introduced March 19, 2001
- Tualatin – 0.13μm process technology
- Introduced July 2001
- Number of transistors 28.1 million
- 32 KB L1 cache
- 256 KB or 512 KB Advanced Transfer L2 cache (integrated)
- 370-pin FC-PGA2 (flip-chip pin grid array) package
- 133 MHz system bus clock rate
- Socket 370
- Family 6 model 11
- Variants
- 1133 MHz (256 KB L2)
- 1133 MHz (512 KB L2)
- 1200 MHz
- 1266 MHz (512 KB L2)
- 1333 MHz
- 1400 MHz (512 KB L2)
- PII Xeon
- Variants
- 400 MHz Introduced June 29, 1998
- 450 MHz (512 KB L2 Cache) Introduced October 6, 1998
- 450 MHz (1MB and 2MB L2 Cache) Introduced January 5, 1999
- Variants
- PIII Xeon
- Introduced October 25, 1999
- Number of transistors: 9.5 million at 0.25μm or 28 million at 0.18μm
- L2 cache is 256 KB, 1MB, or 2MB Advanced Transfer Cache (Integrated)
- Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
- System Bus clock rate 133 MHz (256 KB L2 cache) or 100 MHz (1–2MB L2 cache)
- System Bus width 64 bits
- Addressable memory 64GB
- Used in two-way servers and workstations (256 KB L2) or 4- and 8-way servers (1–2MB L2)
- Family 6 model 10
- Variants
- 500 MHz (0.25μm process) Introduced March 17, 1999
- 550 MHz (0.25μm process) Introduced August 23, 1999
- 600 MHz (0.18μm process, 256 KB L2 cache) Introduced October 25, 1999
- 667 MHz (0.18μm process, 256 KB L2 cache) Introduced October 25, 1999
- 733 MHz (0.18μm process, 256 KB L2 cache) Introduced October 25, 1999
- 800 MHz (0.18μm process, 256 KB L2 cache) Introduced January 12, 2000
- 866 MHz (0.18μm process, 256 KB L2 cache) Introduced April 10, 2000
- 933 MHz (0.18μm process, 256 KB L2 cache)
- 1000 MHz (0.18μm process, 256 KB L2 cache) Introduced August 22, 2000
- 700 MHz (0.18μm process, 1–2MB L2 cache) Introduced May 22, 2000
- Coppermine-128, 0.18μm process technology
- Introduced March, 2000
- Streaming SIMD Extensions (SSE)
- Socket 370, FC-PGA processor package
- Number of transistors: 28.1 million
- 66 MHz system bus clock rate, 100 MHz system bus clock rate from January 3, 2001
- 32 kB L1 cache
- 128 kB Advanced Transfer L2 cache
- Family 6 model 8
- Variants
- 533 MHz
- 566 MHz
- 600 MHz
- 633, 667, 700 MHz Introduced June 26, 2000
- 733, 766 MHz Introduced November 13, 2000
- 800 MHz Introduced January 3, 2001
- 850 MHz Introduced April 9, 2001
- 900 MHz Introduced July 2, 2001
- 950, 1000, 1100 MHz Introduced August 31, 2001
- 550 MHz (Mobile)
- 600, 650 MHz (Mobile) Introduced June 19, 2000
- 700 MHz (Mobile) Introduced September 25, 2000
- 750 MHz (Mobile) Introduced March 19, 2001
- 800 MHz (Mobile)
- 850 MHz (Mobile) Introduced July 2, 2001
- 600 MHz (LV Mobile)
- 500 MHz (ULV Mobile) Introduced January 30, 2001
- 600 MHz (ULV Mobile)
XScale (chronological entry - non-x86 architecture)
- Introduced August 23, 2000
- See main entry
Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 (chronological entries)
- Introduced April 2000 – July 2002
- See main entries
- Tualatin Celeron – 0.13μm process technology
- 32 KB L1 cache
- 256 KB Advanced Transfer L2 cache
- 100 MHz system bus clock rate
- Socket 370
- Family 6 model 11
- Variants
- 1.0 GHz
- 1.1 GHz
- 1.2 GHz
- 1.3 GHz
- 1.4 GHz
- Banias 0.13μm process technology
- Introduced March 2003
- 64 KB L1 cache
- 1MB L2 cache (integrated)
- Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline
- Number of transistors 77 million
- Micro-FCPGA, Micro-FCBGA processor package
- Heart of the ਇੰਟਲ mobile Centrino system
- 400 MHz Netburst-style system bus
- Family 6 model 9
- Variants
- 900 MHz (ultra low voltage)
- 1.0 GHz (ultra low voltage)
- 1.1 GHz (low voltage)
- 1.2 GHz (low voltage)
- 1.3 GHz
- 1.4 GHz
- 1.5 GHz
- 1.6 GHz
- 1.7 GHz
- Dothan 0.09μm (90 nm) process technology
- Introduced May 2004
- 2MB L2 cache
- 140 million transistors
- Revised data prefetch unit
- 400 MHz Netburst-style system bus
- 21W TDP
- Family 6 model 13
- Variants
- 1.00 GHz (Pentium M 723) (ultra low voltage, 5W TDP)
- 1.10 GHz (Pentium M 733) (ultra low voltage, 5W TDP)
- 1.20 GHz (Pentium M 753) (ultra low voltage, 5W TDP)
- 1.30 GHz (Pentium M 718) (low voltage, 10W TDP)
- 1.40 GHz (Pentium M 738) (low voltage, 10W TDP)
- 1.50 GHz (Pentium M 758) (low voltage, 10W TDP)
- 1.60 GHz (Pentium M 778) (low voltage, 10W TDP)
- 1.40 GHz (Pentium M 710)
- 1.50 GHz (Pentium M 715)
- 1.60 GHz (Pentium M 725)
- 1.70 GHz (Pentium M 735)
- 1.80 GHz (Pentium M 745)
- 2.00 GHz (Pentium M 755)
- 2.10 GHz (Pentium M 765)
- Dothan 533 0.09μm (90 nm) process technology
- Introduced Q1 2005
- Same as Dothan except with a 533 MHz NetBurst-style system bus and 27W TDP
- Variants
- 1.60 GHz (Pentium M 730)
- 1.73 GHz (Pentium M 740)
- 1.86 GHz (Pentium M 750)
- 2.00 GHz (Pentium M 760)
- 2.13 GHz (Pentium M 770)
- 2.26 GHz (Pentium M 780)
- Stealey 0.09μm (90 nm) process technology
- Introduced Q2 2007
- 512 KB L2, 3W TDP
- Variants
- 600 MHz (A100)
- 800 MHz (A110)
- Banias-512 0.13μm process technology
- Dothan-1024 90 nm process technology
- 64 KB L1 cache
- 1MB L2 cache (integrated)
- SSE2 SIMD instructions
- No SpeedStep technology, is not part of the 'Centrino' package
- Variants
- 350 – 1.30 GHz
- 350J – 1.30 GHz, with Execute Disable bit
- 360 – 1.40 GHz
- 360J – 1.40 GHz, with Execute Disable bit
- 370 – 1.50 GHz, with Execute Disable bit
- Family 6, Model 13, Stepping 8[5]
- 380 – 1.60 GHz, with Execute Disable bit
- 390 – 1.70 GHz, with Execute Disable bit
- Yonah-1024 65 nm process technology
- 64 KB L1 cache
- 1MB L2 cache (integrated)
- SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit
- No SpeedStep technology, is not part of the 'Centrino' package
- Variants
- 410 – 1.46 GHz
- 420 – 1.60 GHz,
- 423 – 1.06 GHz (ultra low voltage)
- 430 – 1.73 GHz
- 440 – 1.86 GHz
- 443 – 1.20 GHz (ultra low voltage)
- 450 – 2.00 GHz
- Yonah 0.065μm (65 nm) process technology
- Introduced January 2006
- 533/667 MHz front side bus
- 2MB (Shared on Duo) L2 cache
- SSE3 SIMD instructions
- 31W TDP (T versions)
- Family 6, Model 14
- Variants:
- ਇੰਟਲ Core Duo T2700 2.33 GHz
- ਇੰਟਲ Core Duo T2600 2.16 GHz
- ਇੰਟਲ Core Duo T2500 2 GHz
- ਇੰਟਲ Core Duo T2450 2 GHz
- ਇੰਟਲ Core Duo T2400 1.83 GHz
- ਇੰਟਲ Core Duo T2300 1.66 GHz
- ਇੰਟਲ Core Duo T2050 1.6 GHz
- ਇੰਟਲ Core Duo T2300e 1.66 GHz
- ਇੰਟਲ Core Duo T2080 1.73 GHz
- ਇੰਟਲ Core Duo L2500 1.83 GHz (low voltage, 15W TDP)
- ਇੰਟਲ Core Duo L2400 1.66 GHz (low voltage, 15W TDP)
- ਇੰਟਲ Core Duo L2300 1.5 GHz (low voltage, 15W TDP)
- ਇੰਟਲ Core Duo U2500 1.2 GHz (ultra low voltage, 9W TDP)
- ਇੰਟਲ Core Solo T1350 1.86 GHz (533 FSB)
- ਇੰਟਲ Core Solo T1300 1.66 GHz
- ਇੰਟਲ Core Solo T1200 1.5 GHz[6]
- Sossaman 0.065μm (65 nm) process technology
- Introduced March 2006
- Based on Yonah core, with SSE3 SIMD instructions
- 667 MHz frontside bus
- 2MB Shared L2 cache
- Variants
- 2.0 GHz
- 0.18μm process technology (1.40 and 1.50 GHz)
- 0.18μm process technology (1.7 GHz)
- Introduced April 23, 2001
- See the 1.4 and 1.5 chips for details
- 0.18μm process technology (1.6 and 1.8 GHz)
- Introduced July 2, 2001
- See 1.4 and 1.5 chips for details
- Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in Battery Optimized Mode
- Power <1 watt in Battery Optimized Mode
- Used in full-size and then light mobile PCs
- 0.18μm process technology Willamette (1.9 and 2.0 GHz)
- Introduced August 27, 2001
- See 1.4 and 1.5 chips for details
- Family 15 model 1
- Pentium 4 (2 GHz, 2.20 GHz)
- Introduced January 7, 2002
- Pentium 4 (2.4 GHz)
- Introduced April 2, 2002
- 0.13μm process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6, 2.8(OEM),3.0(OEM) GHz)
- Improved branch prediction and other microcodes tweaks
- 512 KB integrated L2 cache
- Number of transistors 55 million
- 400 MHz system bus.
- Family 15 model 2
- 0.13μm process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)
- 533 MHz system bus. (3.06 includes ਇੰਟਲ's Hyper-Threading technology).
- 0.13μm process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)
- 800 MHz system bus (all versions include Hyper-Threading)
- 6500 to 10,000 MIPS
Itanium (chronological entry - new non-x86 architecture)
- Introduced 2001
- See main entry
- Official designation now Xeon, i.e. not "Pentium 4 Xeon"
- Xeon 1.4, 1.5, 1.7 GHz
- Introduced May 21, 2001
- L2 cache was 256 KB Advanced Transfer Cache (Integrated)
- Processor Package Style was Organic Land Grid Array 603 (OLGA 603)
- System Bus clock rate 400 MHz
- SSE2 SIMD Extensions
- Used in high-performance and mid-range dual processor enabled workstations
- Xeon 2.0 GHz and up to 3.6 GHz
- Introduced September 25, 2001
Itanium 2 (chronological entry - new non-x86 architecture)
- Introduced July 2002
- See main entry
Mobile Pentium 4-M
ਸੋਧੋ- 0.13μm process technology
- 55 million transistors
- cache L2 512 KB
- BUS a 400 MHz
- Supports up to 1GB of DDR 266 MHz Memory
- Supports ACPI 2.0 and APM 1.2 System Power Management
- 1.3 V – 1.2 V (SpeedStep)
- Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W
- Sleep Power 5 W (1.2 V)
- Deeper Sleep Power = 2.9 W (1.0 V)
- 1.40 GHz – 23 April 2002
- 1.50 GHz – 23 April 2002
- 1.60 GHz – 4 March 2002
- 1.70 GHz – 4 March 2002
- 1.80 GHz – 23 April 2002
- 1.90 GHz – 24 June 2002
- 2.00 GHz – 24 June 2002
- 2.20 GHz – 16 September 2002
- 2.40 GHz – 14 January 2003
- 2.50 GHz – 16 April 2003
- 2.60 GHz – 11 June 2003
- Introduced September 2003
- EE = "Extreme Edition"
- Built from the Xeon's "Gallatin" core, but with 2MB cache
Pentium 4E
ਸੋਧੋ- Introduced February 2004
- built on 0.09μm (90 nm) process technology Prescott (2.4A, 2.8, 2.8A, 3.0, 3.2, 3.4, 3.6, 3.8) 1MB L2 cache
- 533 MHz system bus (2.4A and 2.8A only)
- 800 MHz system bus (all other models)
- Number of transistors 125 million on 1MB Models
- Number of transistors 169 million on 2MB Models
- Hyper-Threading support is only available on CPUs using the 800 MHz system bus.
- The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater bandwidth.
- 7500 to 11,000 MIPS
- LGA 775 versions are in the 5xx series (32-bit) and 5x1 series (with ਇੰਟਲ 64)
- The 6xx series has 2MB L2 cache and ਇੰਟਲ 64
- New instruction set, not at all related to x86.
- Before the feature was eliminated (Montecito, July 2006) IA-64 processors supported 32-bit x86 in hardware, but slowly (see its 2001 market reception and 2006 architectural changes).[dubious ]
- Code name Merced
- Family 7
- Released May 29, 2001
- 733 MHz and 800 MHz
- 2MB cache
- All recalled and replaced by Itanium 2
- Family 0x1F
- Released July 2002
- 900 MHz – 1.6 GHz
- McKinley 900 MHz 1.5 MB cache, Model 0x0
- McKinley 1 GHz, 3 MB cache, Model 0x0
- Deerfield 1 GHz, 1.5 MB cache, Model 0x1
- Madison 1.3 GHz, 3 MB cache, Model 0x1
- Madison 1.4 GHz, 4 MB cache, Model 0x1
- Madison 1.5 GHz, 6 MB cache, Model 0x1
- Madison 1.67 GHz, 9 MB cache, Model 0x1
- Hondo 1.4 GHz, 4 MB cache, dual-core MCM, Model 0x1
- ਇੰਟਲ Extended Memory 64 Technology
- Mostly compatible with AMD's AMD64 architecture
- Introduced Spring 2004, with the Pentium 4F (D0 and later P4 steppings)
Pentium 4F
ਸੋਧੋ- Prescott-2M built on 0.09μm (90 nm) process technology
- 2.8–3.8 GHz (model numbers 6x0)
- Introduced February 20, 2005
- Same features as Prescott with the addition of:
- Cedar Mill built on 0.065μm (65 nm) process technology
- 3.0–3.6 (model numbers 6x1)
- Introduced January 16, 2006
- Die shrink of Prescott-2M
- Same features as Prescott-2M
- Family 15 Model 4
- Dual-core microprocessor
- No Hyper-Threading
- 800(4×200) MHz front side bus
- LGA 775 (Socket T)
- Smithfield – 90 nm process technology (2.66–3.2 GHz)
- Introduced May 26, 2005
- 2.66–3.2 GHz (model numbers 805–840)
- Number of transistors 230 million
- 1MB × 2 (non-shared, 2MB total) L2 cache
- Cache coherency between cores requires communication over the FSB
- Performance increase of 60% over similarly clocked Prescott
- 2.66 GHz (533 MHz FSB) Pentium D 805 introduced December 2005
- Contains 2x Prescott dies in one package
- Family 15 Model 4
- Presler – 65 nm process technology (2.8–3.6 GHz)
- Introduced January 16, 2006
- 2.8–3.6 GHz (model numbers 915–960)
- Number of transistors 376 million
- 2MB × 2 (non-shared, 4MB total) L2 cache
- Contains 2x Cedar Mill dies in one package
- Variants
- Pentium D 945
- Dual-core microprocessor
- Enabled Hyper-Threading
- 800(4×200) MHz front side bus
- Smithfield – 90 nm process technology (3.2 GHz)
- Variants
- Pentium 840 EE – 3.20 GHz (2 × 1MB L2)
- Variants
- Presler – 65 nm process technology (3.46, 3.73)
- 2MB × 2 (non-shared, 4MB total) L2 cache
- Variants
- Pentium 955 EE – 3.46 GHz, 1066 MHz front side bus
- Pentium 965 EE – 3.73 GHz, 1066 MHz front side bus
- Pentium 969 EE – 3.73 GHz, 1066 MHz front side bus
- Nocona
- Introduced 2004
- Irwindale
- Introduced 2004
- Cranford
- Introduced April 2005
- MP version of Nocona
- Potomac
- Introduced April 2005
- Cranford with 8MB of L3 cache
- Paxville DP (2.8 GHz)
- Introduced October 10, 2005
- Dual-core version of Irwindale, with 4MB of L2 Cache (2MB per core)
- 2.8 GHz
- 800 MT/s front side bus
- Paxville MP – 90 nm process (2.67 – 3.0 GHz)
- Introduced November 1, 2005
- Dual-core Xeon 7000 series
- MP-capable version of Paxville DP
- 2MB of L2 Cache (1MB per core) or 4MB of L2 (2MB per core)
- 667 MT/s FSB or 800 MT/s FSB
- Dempsey – 65 nm process (2.67 – 3.73 GHz)
- Introduced May 23, 2006
- Dual-core Xeon 5000 series
- MP version of Presler
- 667 MT/s or 1066 MT/s FSB
- 4MB of L2 Cache (2MB per core)
- LGA 771 (Socket J).
- Tulsa – 65 nm process (2.5 – 3.4 GHz)
- Introduced August 29, 2006
- Dual-core Xeon 7100-series
- Improved version of Paxville MP
- 667 MT/s or 800 MT/s FSB
- Woodcrest – 65 nm process technology
- Server and Workstation CPU (SMP support for dual CPU system)
- Introduced June 26, 2006
- Dual-core
- ਇੰਟਲ VT-x, multiple OS support
- EIST (Enhanced ਇੰਟਲ SpeedStep Technology) in 5140, 5148LV, 5150, 5160
- Execute Disable Bit
- TXT, enhanced security hardware extensions
- SSSE3 SIMD instructions
- iAMT2 (ਇੰਟਲ Active Management Technology), remotely manage computers
- Variants
- Xeon 5160 – 3.00 GHz (4MB L2, 1333 MHz FSB, 80 W)
- Xeon 5150 – 2.66 GHz (4MB L2, 1333 MHz FSB, 65 W)
- Xeon 5140 – 2.33 GHz (4MB L2, 1333 MHz FSB, 65 W)
- Xeon 5130 – 2.00 GHz (4MB L2, 1333 MHz FSB, 65 W)
- Xeon 5120 – 1.86 GHz (4MB L2, 1066 MHz FSB, 65 W)
- Xeon 5110 – 1.60 GHz (4MB L2, 1066 MHz FSB, 65 W)
- Xeon 5148LV – 2.33 GHz (4MB L2, 1333 MHz FSB, 40 W) (low voltage edition)
- Clovertown – 65 nm process technology
- Server and Workstation CPU (SMP support for dual CPU system)
- Introduced December 13, 2006
- Quad-core
- ਇੰਟਲ VT-x, multiple OS support
- EIST (Enhanced ਇੰਟਲ SpeedStep Technology) in E5365, L5335
- Execute Disable Bit
- TXT, enhanced security hardware extensions
- SSSE3 SIMD instructions
- iAMT2 (ਇੰਟਲ Active Management Technology), remotely manage computers
- Variants
- Xeon X5355 – 2.66 GHz (2×4MB L2, 1333 MHz FSB, 105 W)
- Xeon E5345 – 2.33 GHz (2×4MB L2, 1333 MHz FSB, 80 W)
- Xeon E5335 – 2.00 GHz (2×4MB L2, 1333 MHz FSB, 80 W)
- Xeon E5320 – 1.86 GHz (2×4MB L2, 1066 MHz FSB, 65 W)
- Xeon E5310 – 1.60 GHz (2×4MB L2, 1066 MHz FSB, 65 W)
- Xeon L5320 – 1.86 GHz (2×4MB L2, 1066 MHz FSB, 50 W) (low voltage edition)
- Conroe – 65 nm process technology
- Desktop CPU (SMP support restricted to 2 CPUs)
- Two cores on one die
- Introduced July 27, 2006
- SSSE3 SIMD instructions
- Number of transistors: 291 million
- 64 KB of L1 cache per core (32+32 KB 8-way)
- ਇੰਟਲ VT-x, multiple OS support
- TXT, enhanced security hardware extensions
- Execute Disable Bit
- EIST (Enhanced ਇੰਟਲ SpeedStep Technology)
- iAMT2 (ਇੰਟਲ Active Management Technology), remotely manage computers
- LGA 775
- Variants
- Core 2 Duo E6850 – 3.00 GHz (4MB L2, 1333 MHz FSB)
- Core 2 Duo E6800 – 2.93 GHz (4MB L2, 1066 MHz FSB)
- Core 2 Duo E6750 – 2.67 GHz (4MB L2, 1333 MHz FSB, 65W)
- Core 2 Duo E6700 – 2.67 GHz (4MB L2, 1066 MHz FSB)
- Core 2 Duo E6600 – 2.40 GHz (4MB L2, 1066 MHz FSB, 65W)
- Core 2 Duo E6550 – 2.33 GHz (4MB L2, 1333 MHz FSB)
- Core 2 Duo E6420 – 2.13 GHz (4MB L2, 1066 MHz FSB)
- Core 2 Duo E6400 – 2.13 GHz (2MB L2, 1066 MHz FSB)
- Core 2 Duo E6320 – 1.86 GHz (4MB L2, 1066 MHz FSB) Family 6, Model 15, Stepping 6
- Core 2 Duo E6300 – 1.86 GHz (2MB L2, 1066 MHz FSB)
- Conroe XE – 65 nm process technology
- Desktop Extreme Edition CPU (SMP support restricted to 2 CPUs)
- Introduced July 27, 2006
- same features as Conroe
- LGA 775
- Variants
- Core 2 Extreme X6800 – 2.93 GHz (4MB L2, 1066 MHz FSB)
- Allendale – 65 nm process technology
- Desktop CPU (SMP support restricted to 2 CPUs)
- Two CPUs on one die
- Introduced January 21, 2007
- SSSE3 SIMD instructions
- Number of transistors 167 million
- TXT, enhanced security hardware extensions
- Execute Disable Bit
- EIST (Enhanced ਇੰਟਲ SpeedStep Technology)
- iAMT2 (ਇੰਟਲ Active Management Technology), remotely manage computers
- LGA 775
- Variants
- Core 2 Duo E4700 – 2.60 GHz (2MB L2, 800 MHz FSB)
- Core 2 Duo E4600 – 2.40 GHz (2MB L2, 800 MHz FSB)
- Core 2 Duo E4500 – 2.20 GHz (2MB L2, 800 MHz FSB)
- Core 2 Duo E4400 – 2.00 GHz (2MB L2, 800 MHz FSB)
- Core 2 Duo E4300 – 1.80 GHz (2MB L2, 800 MHz FSB) Family 6, Model 15, Stepping 2
- Merom – 65 nm process technology
- Mobile CPU (SMP support restricted to 2 CPUs)
- Introduced July 27, 2006
- Family 6, Model 15
- same features as Conroe
- Socket M / Socket P
- Variants
- Core 2 Duo T7800 – 2.60 GHz (4MB L2, 800 MHz FSB) (Santa Rosa platform)
- Core 2 Duo T7700 – 2.40 GHz (4MB L2, 800 MHz FSB)
- Core 2 Duo T7600 – 2.33 GHz (4MB L2, 667 MHz FSB)
- Core 2 Duo T7500 – 2.20 GHz (4MB L2, 800 MHz FSB)
- Core 2 Duo T7400 – 2.16 GHz (4MB L2, 667 MHz FSB)
- Core 2 Duo T7300 – 2.00 GHz (4MB L2, 800 MHz FSB)
- Core 2 Duo T7250 – 2.00 GHz (2MB L2, 800 MHz FSB)
- Core 2 Duo T7200 – 2.00 GHz (4MB L2, 667 MHz FSB)
- Core 2 Duo T7100 – 1.80 GHz (2MB L2, 800 MHz FSB)
- Core 2 Duo T5600 – 1.83 GHz (2MB L2, 667 MHz FSB) Family 6, Model 15, Stepping 6
- Core 2 Duo T5550 – 1.83 GHz (2MB L2, 667 MHz FSB, no VT)
- Core 2 Duo T5500 – 1.66 GHz (2MB L2, 667 MHz FSB, no VT)
- Core 2 Duo T5470 – 1.60 GHz (2MB L2, 800 MHz FSB, no VT) Family 6, Model 15, Stepping 13
- Core 2 Duo T5450 – 1.66 GHz (2MB L2, 667 MHz FSB, no VT)
- Core 2 Duo T5300 – 1.73 GHz (2MB L2, 533 MHz FSB, no VT)
- Core 2 Duo T5270 – 1.40 GHz (2MB L2, 800 MHz FSB, no VT)
- Core 2 Duo T5250 – 1.50 GHz (2MB L2, 667 MHz FSB, no VT)
- Core 2 Duo T5200 – 1.60 GHz (2MB L2, 533 MHz FSB, no VT)
- Core 2 Duo L7500 – 1.60 GHz (4MB L2, 800 MHz FSB) (low voltage)
- Core 2 Duo L7400 – 1.50 GHz (4MB L2, 667 MHz FSB) (low voltage)
- Core 2 Duo L7300 – 1.40 GHz (4MB L2, 800 MHz FSB) (low voltage)
- Core 2 Duo L7200 – 1.33 GHz (4MB L2, 667 MHz FSB) (low voltage)
- Core 2 Duo U7700 – 1.33 GHz (2MB L2, 533 MHz FSB) (ultra low voltage)
- Core 2 Duo U7600 – 1.20 GHz (2MB L2, 533 MHz FSB) (ultra low voltage)
- Core 2 Duo U7500 – 1.06 GHz (2MB L2, 533 MHz FSB) (ultra low voltage)
- Kentsfield – 65 nm process technology
- Two dual-core CPU dies in one package.
- Desktop CPU quad-core (SMP support restricted to 4 CPUs)
- Introduced December 13, 2006
- same features as Conroe but with 4 CPU cores
- Number of transistors 586 million
- LGA 775
- Family 6, Model 15, Stepping 11
- Variants
- Core 2 Extreme QX6850 – 3 GHz (2×4MB L2 Cache, 1333 MHz FSB)
- Core 2 Extreme QX6800 – 2.93 GHz (2×4MB L2 Cache, 1066 MHz FSB) (April 9, 2007)
- Core 2 Extreme QX6700 – 2.66 GHz (2×4MB L2 Cache, 1066 MHz FSB) (November 14, 2006)
- Core 2 Quad Q6700 – 2.66 GHz (2×4MB L2 Cache, 1066 MHz FSB) (July 22, 2007)
- Core 2 Quad Q6600 – 2.40 GHz (2×4MB L2 Cache, 1066 MHz FSB) (January 7, 2007)
- Wolfdale – 45 nm process technology
- Die shrink of Conroe
- Same features as Conroe with the addition of:
- Number of transistors 410 million
- Variants
- Core 2 Duo E8600 – 3.33 GHz (6MB L2, 1333 MHz FSB)
- Core 2 Duo E8500 – 3.16 GHz (6MB L2, 1333 MHz FSB)
- Core 2 Duo E8435 – 3.07 GHz (6MB L2, 1066 MHz FSB)
- Core 2 Duo E8400 – 3.00 GHz (6MB L2, 1333 MHz FSB)
- Core 2 Duo E8335 – 2.93 GHz (6MB L2, 1066 MHz FSB)
- Core 2 Duo E8300 – 2.83 GHz (6MB L2, 1333 MHz FSB)
- Core 2 Duo E8235 – 2.80 GHz (6MB L2, 1066 MHz FSB)
- Core 2 Duo E8200 – 2.66 GHz (6MB L2, 1333 MHz FSB)
- Core 2 Duo E8135 – 2.66 GHz (6MB L2, 1066 MHz FSB)
- Core 2 Duo E8190 – 2.66 GHz (6MB L2, 1333 MHz FSB, no TXT, no VT)
- Wolfdale-3M – 45 nm process technology
- ਇੰਟਲ Trusted Execution Technology
- Variants
- Core 2 Duo E7600 – 3.06 GHz (3MB L2, 1066 MHz FSB)
- Core 2 Duo E7500 – 2.93 GHz (3MB L2, 1066 MHz FSB)
- Core 2 Duo E7400 – 2.80 GHz (3MB L2, 1066 MHz FSB)
- Core 2 Duo E7300 – 2.66 GHz (3MB L2, 1066 MHz FSB)
- Core 2 Duo E7200 – 2.53 GHz (3MB L2, 1066 MHz FSB)
- Yorkfield – 45 nm process technology
- Quad-core CPU
- Die shrink of Kentsfield
- Contains 2x Wolfdale dual-core dies in one package
- Same features as Wolfdale
- Number of transistors 820 million
- Variants
- Core 2 Extreme QX9770 – 3.20 GHz (2×6MB L2, 1600 MHz FSB)
- Core 2 Extreme QX9650 – 3.00 GHz (2×6MB L2, 1333 MHz FSB)
- Core 2 Quad Q9705 – 3.16 GHz (2×3MB L2, 1333 MHz FSB)
- Core 2 Quad Q9700 – 3.16 GHz (2×3MB L2, 1333 MHz FSB)
- Core 2 Quad Q9650 – 3 GHz (2×6MB L2, 1333 MHz FSB)
- Core 2 Quad Q9550 – 2.83 GHz (2×6MB L2, 1333 MHz FSB, 95W TDP)
- Core 2 Quad Q9550s – 2.83 GHz (2×6MB L2, 1333 MHz FSB, 65W TDP)
- Core 2 Quad Q9450 – 2.66 GHz (2×6MB L2, 1333 MHz FSB, 95W TDP)
- Core 2 Quad Q9505 – 2.83 GHz (2×3MB L2, 1333 MHz FSB, 95W TDP)
- Core 2 Quad Q9505s – 2.83 GHz (2×3MB L2, 1333 MHz FSB, 65W TDP)
- Core 2 Quad Q9500 – 2.83 GHz (2×3MB L2, 1333 MHz FSB, 95W TDP, no TXT)
- Core 2 Quad Q9400 – 2.66 GHz (2×3MB L2, 1333 MHz FSB, 95W TDP)
- Core 2 Quad Q9400s – 2.66 GHz (2×3MB L2, 1333 MHz FSB, 65W TDP)
- Core 2 Quad Q9300 – 2.50 GHz (2×3MB L2, 1333 MHz FSB, 95W TDP)
- Core 2 Quad Q8400 – 2.66 GHz (2×2MB L2, 1333 MHz FSB, 95W TDP)
- Core 2 Quad Q8400s – 2.66 GHz (2×2MB L2, 1333 MHz FSB, 65W TDP)
- Core 2 Quad Q8300 – 2.50 GHz (2×2MB L2, 1333 MHz FSB, 95W TDP)
- Core 2 Quad Q8300s – 2.50 GHz (2×2MB L2, 1333 MHz FSB, 65W TDP)
- Core 2 Quad Q8200 – 2.33 GHz (2×2MB L2, 1333 MHz FSB, 95W TDP)
- Core 2 Quad Q8200s – 2.33 GHz (2×2MB L2, 1333 MHz FSB, 65W TDP)
- Core 2 Quad Q7600 – 2.70 GHz (2×1MB L2, 800 MHz FSB, no SSE4) (no Q7600 listed here[permanent dead link])
- ਇੰਟਲ Core2 Quad Mobile Processor Family – 45 nm process technology
- Quad-core CPU
- Variants
- Core 2 Quad Q9100 – 2.26 GHz (2×6MB L2, 1066 MHz FSB, 45W TDP)
- Core 2 Quad Q9000 – 2.00 GHz (2×3MB L2, 1066 MHz FSB, 45W TDP)
- Allendale – 65 nm process technology
- Desktop CPU (SMP support restricted to 2 CPUs)
- Two cores on one die
- Introduced January 21, 2007
- SSSE3 SIMD instructions
- Number of transistors 167 million
- TXT, enhanced security hardware extensions
- Execute Disable Bit
- EIST (Enhanced ਇੰਟਲ SpeedStep Technology)
- Variants
- ਇੰਟਲ Pentium E2220 – 2.40 GHz (1MB L2, 800 MHz FSB)
- ਇੰਟਲ Pentium E2200 – 2.20 GHz (1MB L2, 800 MHz FSB)
- ਇੰਟਲ Pentium E2180 – 2.00 GHz (1MB L2, 800 MHz FSB)
- ਇੰਟਲ Pentium E2160 – 1.80 GHz (1MB L2, 800 MHz FSB)
- ਇੰਟਲ Pentium E2140 – 1.60 GHz (1MB L2, 800 MHz FSB)
- Wolfdale-3M 45 nm process technology
- ਇੰਟਲ Pentium E6800 – 3.33 GHz (2MB L2,1066 MHz FSB)
- ਇੰਟਲ Pentium E6700 – 3.20 GHz (2MB L2,1066 MHz FSB)
- ਇੰਟਲ Pentium E6600 – 3.06 GHz (2MB L2,1066 MHz FSB)
- ਇੰਟਲ Pentium E6500 – 2.93 GHz (2MB L2,1066 MHz FSB)
- ਇੰਟਲ Pentium E6300 – 2.80 GHz (2MB L2,1066 MHz FSB)
- ਇੰਟਲ Pentium E5800 – 3.20 GHz (2MB L2, 800 MHz FSB)
- ਇੰਟਲ Pentium E5700 – 3.00 GHz (2MB L2, 800 MHz FSB)
- ਇੰਟਲ Pentium E5500 – 2.80 GHz (2MB L2, 800 MHz FSB)
- ਇੰਟਲ Pentium E5400 – 2.70 GHz (2MB L2, 800 MHz FSB)
- ਇੰਟਲ Pentium E5300 – 2.60 GHz (2MB L2, 800 MHz FSB)
- ਇੰਟਲ Pentium E5200 – 2.50 GHz (2MB L2, 800 MHz FSB)
- ਇੰਟਲ Pentium E2210 – 2.20 GHz (1MB L2, 800 MHz FSB)
- Allendale – 65 nm process technology
- Variants
- ਇੰਟਲ Celeron E1600 – 2.40 GHz (512 KB L2, 800 MHz FSB)
- ਇੰਟਲ Celeron E1500 – 2.20 GHz (512 KB L2, 800 MHz FSB)
- ਇੰਟਲ Celeron E1400 – 2.00 GHz (512 KB L2, 800 MHz FSB)
- ਇੰਟਲ Celeron E1300 – 1.80 GHz (512 KB L2, 800 MHz FSB) (does it exist?)[ਹਵਾਲਾ ਲੋੜੀਂਦਾ]
- ਇੰਟਲ Celeron E1200 – 1.60 GHz (512 KB L2, 800 MHz FSB)
- Variants
- Wolfdale-3M – 45 nm process technology
- Variants
- ਇੰਟਲ Celeron E3500 – 2.70 GHz (1MB L2, 800 MHz FSB)
- ਇੰਟਲ Celeron E3400 – 2.60 GHz (1MB L2, 800 MHz FSB)
- ਇੰਟਲ Celeron E3300 – 2.50 GHz (1MB L2, 800 MHz FSB)
- ਇੰਟਲ Celeron E3200 – 2.40 GHz (1MB L2, 800 MHz FSB)
- Variants
- Conroe-L – 65 nm process technology
- Variants
- ਇੰਟਲ Celeron 450 – 2.20 GHz (512 KB L2, 800 MHz FSB)
- ਇੰਟਲ Celeron 440 – 2.00 GHz (512 KB L2, 800 MHz FSB)
- ਇੰਟਲ Celeron 430 – 1.80 GHz (512 KB L2, 800 MHz FSB)
- ਇੰਟਲ Celeron 420 – 1.60 GHz (512 KB L2, 800 MHz FSB)
- ਇੰਟਲ Celeron 220 – 1.20 GHz (512 KB L2, 533 MHz FSB)
- Variants
- Conroe-CL – 65 nm process technology
- LGA 771 package
- Variants
- ਇੰਟਲ Celeron 445 – 1.87 GHz (512 KB L2, 1066 MHz FSB)
- 667 MHz FSB
- 575 – 2.00GHz
- 585 – 2.16GHz
- Clarkdale – 32 nm process technology
- 2 physical cores/2 threads
- 3MB L3 cache
- Introduced January 2010
- Socket 1156 LGA
- 2-channel DDR3
- Integrated HD GPU
- Variants
- G6950 – 2.8 GHz (no Hyper-Threading)[7]
- G6960 – 2.933 GHz (no Hyper-Threading)
- Clarkdale – 32 nm process technology
- 2 physical cores/4 threads
- 64 Kb L1 cache
- 512 Kb L2 cache
- 4MB L3 cache
- Introduced in January 7, 2010
- Socket 1156 LGA
- 2-channel DDR3
- Integrated HD GPU
- Variants
- 530 – 2.93 GHz Hyper-Threading
- 540 – 3.06 GHz Hyper-Threading
- 550 – 3.2 GHz Hyper-Threading
- 560 – 3.33 GHz Hyper-Threading
- Lynnfield – 45 nm process technology
- 4 physical cores
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 8MB common L3 cache
- Introduced September 8, 2009
- Family 6 Model E (Ext. Model 1E)
- Socket 1156 LGA
- 2-channel DDR3
- Variants
- 750S – 2.40 GHz/3.20 GHz Turbo Boost
- 750 – 2.66 GHz/3.20 GHz Turbo Boost
- 760 – 2.80 GHz/3.33 GHz Turbo Boost
- Clarkdale – 32 nm process technology
- 2 physical cores/4 threads
- 64 Kb L1 cache
- 512 Kb L2 cache
- 4MB L3 cache
- Introduced January, 2010
- Socket 1156 LGA
- 2-channel DDR3
- Integrated HD GPU
- AES Support
- Variants
- 650/655K – 3.2 GHz Hyper-Threading Turbo Boost
- 660/661 – 3.33 GHz Hyper-Threading Turbo Boost
- 670 – 3.46 GHz Hyper-Threading Turbo Boost
- 680 – 3.60 GHz Hyper-Threading Turbo Boost
- Bloomfield – 45 nm process technology
- 4 physical cores
- 256 KB L2 cache
- 8MB L3 cache
- Front side bus replaced with QuickPath up to 6.4GT/s
- Hyper-Threading is again included. This had previously been removed at the introduction of Core line
- 781 million transistors
- ਇੰਟਲ Turbo Boost Technology
- TDP 130W
- Introduced November 17, 2008
- Socket 1366 LGA
- 3-channel DDR3
- Variants
- 975 (extreme edition) – 3.33 GHz/3.60 GHz Turbo Boost
- 965 (extreme edition) – 3.20 GHz/3.46 GHz Turbo Boost
- 960 – 3.20 GHz/3.46 GHz Turbo Boost
- 950 – 3.06 GHz/3.33 GHz Turbo Boost
- 940 – 2.93 GHz/3.20 GHz Turbo Boost
- 930 – 2.80 GHz/3.06 GHz Turbo Boost
- 920 – 2.66 GHz/2.93 GHz Turbo Boost
- Lynnfield – 45 nm process technology
- 4 physical cores
- 256 KB L2 cache
- 8MB L3 cache
- No QuickPath, instead compatible with slower DMI interface
- Hyper-Threading is included
- Introduced September 8, 2009
- Socket 1156 LGA
- 2-channel DDR3
- Variants
- 880 – 3.06 GHz/3.73 GHz Turbo Boost (TDP 95W)
- 870/875K – 2.93 GHz/3.60 GHz Turbo Boost (TDP 95W)
- 870S – 2.67 GHz/3.60 GHz Turbo Boost (TDP 82W)
- 860 – 2.80 GHz/3.46 GHz Turbo Boost (TDP 95W)
- 860S – 2.53 GHz/3.46 GHz Turbo Boost (TDP 82W)
TODO: Westmere
- Gulftown – 32 nm process technology
- 6 physical cores
- 256 KB L2 cache
- 12MB L3 cache
- Front side bus replaced with QuickPath up to 6.4GT/s
- Hyper-Threading is included
- ਇੰਟਲ Turbo Boost Technology
- Socket 1366 LGA
- TDP 130W
- Introduced 16 March 2010
- Variants
- 990X Extreme Edition – 3.46 GHz/3.73 GHz Turbo Boost
- 980X Extreme Edition – 3.33 GHz/3.60 GHz Turbo Boost
- 970 – 3.20 GHz/3.46 GHz Turbo Boost
- Clarksfield – ਇੰਟਲ Core i7 Mobile Processor Family – 45 nm process technology
- 4 physical cores
- Hyper-Threading is included
- ਇੰਟਲ Turbo Boost Technology
- Variants
- 940XM Extreme Edition – 2.13 GHz/3.33 GHz Turbo Boost (8MB L3, TDP 55W)
- 920XM Extreme Edition – 2.00 GHz/3.20 GHz Turbo Boost (8MB L3, TDP 55W)
- 840QM – 1.86 GHz/3.20 GHz Turbo Boost (8MB L3, TDP 45W)
- 820QM – 1.73 GHz/3.06 GHz Turbo Boost (8MB L3, TDP 45W)
- 740QM – 1.73 GHz/2.93 GHz Turbo Boost (6MB L3, TDP 45W)
- 720QM – 1.60 GHz/2.80 GHz Turbo Boost (6MB L3, TDP 45W)
- Gainestown – 45 nm process technology
- Same processor dies as Bloomfield
- 256 KB L2 cache
- 8MB L3 cache, 4MB may be disabled
- QuickPath up to 6.4GT/s
- Hyper-Threading is included in some models
- 781 million transistors
- Introduced March 29, 2009
- Variants
- W5590,X5570, X5570, X5560, X5550, E5540, E5530, L5530, E5520, L5520, L5518 – 4 cores, 8MB L3 cache, HT
- E5506, L5506, E5504 – 4 cores, 4MB L3 cache, no HT
- L5508, E5502, E5502 – 2 cores, 4MB L3 cache, no HT
64-bit processors: ਇੰਟਲ 64 – Sandy Bridge / Ivy Bridge microarchitecture
ਸੋਧੋਇਸ ਲੇਖ ਦੀ ਸਮੱਗਰੀ ਪੁਰਾਣੀ ਹੈ। ਕਿਰਪਾ ਕਰਕੇ ਇਸ ਲੇਖ ਨੂੰ ਨਵੀਂ ਮਿਲੀ ਜਾਣਕਾਰੀ ਭਾਵ ਕਿ ਨਵੀਆਂ ਘਟਨਾਵਾਂ ਦੀ ਜਾਣਕਾਰੀ ਜੋੜ ਕੇ ਬਿਹਤਰ ਬਣਾਉਣ ਵਿੱਚ ਮਦਦ ਕਰੋ। (June 2013) |
- Sandy Bridge – 32 nm process technology
- 2 physical cores/2 threads (500 series), 1 physical core/1 thread (model G440) or 1 physical core/2 threads (models G460 & G465)
- 2MB L3 cache (500 series), 1MB (model G440) or 1.5MB (models G460 & G465)
- Introduced 3rd quarter, 2011
- Socket 1155 LGA
- 2-channel DDR3-1066
- 400 series has max TDP of 35W
- 500-series variants ending in 'T' have a peak TDP of 35W, others – 65W
- Integrated GPU
- All variants have peak GPU turbo frequencies of 1 GHz
- Variants in the 400 series have GPUs running at a base frequency of 650 MHz
- Variants in the 500 series ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz
- All variants have 6 GPU execution units
- Variants
- G440 – 1.6 GHz
- G460 – 1.8 GHz
- G465 – 1.9 GHz
- G530T – 2.0 GHz
- G540T – 2.1 GHz
- G550T – 2.2 GHz
- G530 – 2.4 GHz
- G540 – 2.5 GHz
- G550 – 2.6 GHz
- G555 – 2.7 GHz
- Sandy Bridge – 32 nm process technology
- 2 physical cores/2 threads
- 3MB L3 cache
- 624 million transistors
- Introduced May, 2011
- Socket 1155 LGA
- 2-channel DDR3-1333 (800 series) or DDR3-1066 (600 series)
- Variants ending in 'T' have a peak TDP of 35W, others 65W
- Integrated GPU (HD 2000)
- All variants have peak GPU turbo frequencies of 1.1 GHz
- Variants ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz
- All variants have 6 GPU execution units
- Variants
- G620T – 2.2 GHz
- G630T – 2.3 GHz
- G640T – 2.4 GHz
- G645T – 2.5 GHz
- G860T – 2.6 GHz
- G620 – 2.6 GHz
- G622 – 2.6 GHz
- G630 – 2.7 GHz
- G632 – 2.7 GHz
- G640 – 2.8 GHz
- G840 – 2.8 GHz
- G645 – 2.9 GHz
- G850 – 2.9 GHz
- G860 – 3.0 GHz
- G870 – 3.1 GHz
- Ivy Bridge – 22 nm Tri-gate transistor process technology
- 2 physical cores/2 threads
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 3MB L3 cache
- Introduced September, 2012
- Socket 1155 LGA
- 2-channel DDR3-1333 for G2000 series
- 2-channel DDR3-1600 for G2100 series
- All variants have GPU base frequencies of 650 MHz and peak GPU turbo frequencies of 1.05 GHz
- Variants ending in 'T' have a peak TDP of 35W, others – TDP of 55W
- Variants
- G2020T – 2.5 GHz
- G2030T – 2.6 GHz
- G2100T – 2.6 GHz
- G2120T – 2.7 GHz
- G2020 – 2.9 GHz
- G2030 – 3.0 GHz
- G2120 – 3.1 GHz
- G2130 – 3.2 GHz
- G2140 – 3.3 GHz
- Sandy Bridge – 32 nm process technology
- 2 physical cores/4 threads
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 3MB L3 cache
- 624 million transistors
- Introduced January, 2012
- Socket 1155 LGA
- 2-channel DDR3-1333
- Variants ending in 'T' have a peak TDP of 35W, others 65W
- Integrated GPU
- All variants have peak GPU turbo frequencies of 1.1 GHz
- Variants ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz
- Variants ending in '5' have ਇੰਟਲ HD Graphics 3000 (12 execution units); others have ਇੰਟਲ HD Graphics 2000 (6 execution units)
- Variants
- i3-2100T – 2.5 GHz
- i3-2120T – 2.6 GHz
- i3-2100 – 3.1 GHz
- i3-2102 – 3.1 GHz
- i3-2105 – 3.1 GHz
- i3-2120 – 3.3 GHz
- i3-2125 – 3.3 GHz
- i3-2130 – 3.4 GHz
- Ivy Bridge – 22 nm Tri-gate transistor process technology
- 2 physical cores/4 threads
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 3MB L3 cache
- Introduced September, 2012
- Socket 1155 LGA
- 2-channel DDR3-1600
- Variants ending in '5' have ਇੰਟਲ HD Graphics 4000; others have ਇੰਟਲ HD Graphics 2500
- All variants have GPU base frequencies of 650 MHz and peak GPU turbo frequencies of 1.05 GHz
- TDP 55W
- Variants
- i3-3220T – 2.8 GHz
- i3-3240T – 2.9 GHz
- i3-3210 – 3.2 GHz
- i3-3220 – 3.3 GHz
- i3-3225 – 3.3 GHz
- i3-3240 – 3.4 GHz
- Sandy Bridge – 32 nm process technology
- 4 physical cores/4 threads (except for i5-2390T which has 2 physical cores/4 threads)
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 6MB L3 cache (except for i5-2390T which has 3MB)
- 995 million transistors
- Introduced January, 2011
- Socket 1155 LGA
- 2-channel DDR3-1333
- Variants ending in 'S' have a peak TDP of 65W, others – 95W except where noted
- Variants ending in 'K' have unlocked multipliers; others cannot be overclocked
- Integrated GPU
- i5-2500T has a peak GPU turbo frequency of 1.25 GHz, others 1.1 GHz
- Variants ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz
- Variants ending in '5' or 'K' have ਇੰਟਲ HD Graphics 3000 (12 execution units), except i5-2550K which has no GPU; others have ਇੰਟਲ HD Graphics 2000 (6 execution units)
- Variants ending in 'P' and the i5-2550K have no GPU
- Variants
- i5-2390T – 2.7 GHz/3.5 GHz Turbo Boost (35W max TDP)
- i5-2500T – 2.3 GHz/3.3 GHz Turbo Boost (45W max TDP)
- i5-2400S – 2.5 GHz/3.3 GHz Turbo Boost
- i5-2405S – 2.5 GHz/3.3 GHz Turbo Boost
- i5-2500S – 2.7 GHz/3.7 GHz Turbo Boost
- i5-2300 – 2.8 GHz/3.1 GHz Turbo Boost
- i5-2310 – 2.9 GHz/3.2 GHz Turbo Boost
- i5-2320 – 3.0 GHz/3.3 GHz Turbo Boost
- i5-2380P – 3.1 GHz/3.4 GHz Turbo Boost
- i5-2400 – 3.1 GHz/3.4 GHz Turbo Boost
- i5-2450P – 3.2 GHz/3.5 GHz Turbo Boost
- i5-2500 – 3.3 GHz/3.7 GHz Turbo Boost
- i5-2500K – 3.3 GHz/3.7 GHz Turbo Boost
- i5-2550K – 3.4 GHz/3.8 GHz Turbo Boost
- Ivy Bridge – 22 nm Tri-gate transistor process technology
- 4 physical cores/4 threads (except for i5-3470T which has 2 physical cores/4 threads)
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 6MB L3 cache (except for i5-3470T which has 3MB)
- Introduced April, 2012
- Socket 1155 LGA
- 2-channel DDR3-1600
- Variants ending in 'S' have a peak TDP of 65W, Variants ending in 'T' have a peak TDP of 35 or 45W (see variants), others – 77W except where noted
- Variants ending in 'K' have unlocked multipliers; others cannot be overclocked
- Variants ending in 'P' have no integrated GPU; others have ਇੰਟਲ HD Graphics 2500 or ਇੰਟਲ HD Graphics 4000 (i5-3475S and i5-3570K only)
- Variants
- i5-3470T – 2.9 GHz/3.6 GHz max Turbo Boost (35W TDP)
- i5-3570T – 2.3 GHz/3.3 GHz max Turbo Boost (45W TDP)
- i5-3330S – 2.7 GHz/3.2 GHz max Turbo Boost
- i5-3450S – 2.8 GHz/3.5 GHz max Turbo Boost
- i5-3470S – 2.9 GHz/3.6 GHz max Turbo Boost
- i5-3475S – 2.9 GHz/3.6 GHz max Turbo Boost
- i5-3550S – 3.0 GHz/3.7 GHz max Turbo Boost
- i5-3570S – 3.1 GHz/3.8 GHz max Turbo Boost
- i5-3330 – 3.0 GHz/3.2 GHz max Turbo Boost
- i5-3350P – 3.1 GHz/3.3 GHz max Turbo Boost (69W TDP)
- i5-3450 – 3.1 GHz/3.5 GHz max Turbo Boost
- i5-3470 – 3.2 GHz/3.6 GHz max Turbo Boost
- i5-3550 – 3.3 GHz/3.7 GHz max Turbo Boost
- i5-3570 – 3.4 GHz/3.8 GHz max Turbo Boost
- i5-3570K – 3.4 GHz/3.8 GHz max Turbo Boost
- Sandy Bridge – 32 nm process technology
- 4 physical cores/8 threads
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 8MB L3 cache
- 995 million transistors
- Introduced January, 2011
- Socket 1155 LGA
- 2-channel DDR3-1333
- Variants ending in 'S' have a peak TDP of 65W, others – 95W
- Variants ending in 'K' have unlocked multipliers; others cannot be overclocked
- Integrated GPU
- All variants have base GPU frequencies of 850 MHz and peak GPU turbo frequencies of 1.35 GHz
- Variants ending in 'K' have ਇੰਟਲ HD Graphics 3000 (12 execution units); others have ਇੰਟਲ HD Graphics 2000 (6 execution units)
- Variants
- i7-2600S – 2.8 GHz/3.8 GHz Turbo Boost
- i7-2600 – 3.4 GHz/3.8 GHz Turbo Boost
- i7-2600K – 3.4 GHz/3.8 GHz Turbo Boost
- i7-2700K – 3.5 GHz/3.9 GHz Turbo Boost
- Sandy Bridge-E – 32 nm process technology
- Up to 8 physical cores/16 threads depending on model number
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- Up to 20MB L3 cache depending on model number
- 2270 million transistors
- Introduced November, 2011
- Socket 2011 LGA
- 4-channel DDR3-1600
- All variants have a peak TDP of 130W
- No integrated GPU
- Variants
- i7-3820 – 3.6 GHz/3.8 GHz Turbo Boost, 4 cores, 10MB L3 cache
- i7-3930K – 3.2 GHz/3.8 GHz Turbo Boost, 6 cores, 12MB L3 cache
- i7-3960X – 3.3 GHz/3.9 GHz Turbo Boost, 6 cores, 15MB L3 cache
- i7-3970X – 3.5 GHz/4.0 GHz Turbo Boost, 6 cores, 15MB L3 cache
- Ivy Bridge – 22 nm Tri-gate transistor process technology
- 4 physical cores/8 threads
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 8MB L3 cache
- Introduced April, 2012
- Socket 1155 LGA
- 2-channel DDR3-1600
- Variants ending in 'S' have a peak TDP of 65W, variants ending in 'T' have a peak TDP of 45W, others – 77W
- Variants ending in 'K' have unlocked multipliers; others cannot be overclocked
- Integrated GPU ਇੰਟਲ HD Graphics 4000
- Variants
- i7-3770T – 2.5 GHz/3.7 GHz Turbo Boost
- i7-3770S – 3.1 GHz/3.9 GHz Turbo Boost
- i7-3770 – 3.4 GHz/3.9 GHz Turbo Boost
- i7-3770K – 3.5 GHz/3.9 GHz Turbo Boost
- 2007: Teraflops Research Chip, an 80 cores processor prototype.
- 2009: Single-chip Cloud Computer, a research microprocessor containing the most ਇੰਟਲ Architecture cores ever integrated on a silicon CPU chip – 48 cores.
ਇੰਟਲ 805xx product codes
ਸੋਧੋਇੰਟਲ discontinued the use of part numbers such as 80486 in the marketing of mainstream x86-architecture microprocessors with the introduction of the Pentium brand in 1993. However, numerical codes, in the 805xx range, continued to be assigned to these processors for internal and part numbering uses. The following is a list of such product codes in numerical order:
| Product code | Marketing name(s) | Codename(s) |
|---|---|---|
| 80500 | Pentium | P5 (A-step) |
| 80501 | Pentium | P5 |
| 80502 | Pentium | P54C, P54CS |
| 80503 | Pentium with MMX Technology | P55C, Tillamook |
| 80521 | Pentium Pro | P6 |
| 80522 | Pentium II | Klamath |
| 80523 | Pentium II, Celeron, Pentium II Xeon | Deschutes, Covington, Drake |
| 80524 | Pentium II, Celeron | Dixon, Mendocino |
| 80525 | Pentium III, Pentium III Xeon | Katmai, Tanner |
| 80526 | Pentium III, Celeron, Pentium III Xeon | Coppermine, Cascades |
| 80528 | Pentium 4, Xeon | Willamette (Socket 423), Foster |
| 80529 | canceled | Timna |
| 80530 | Pentium III, Celeron | Tualatin |
| 80531 | Pentium 4, Celeron | Willamette (Socket 478) |
| 80532 | Pentium 4, Celeron, Xeon | Northwood, Prestonia, Gallatin |
| 80533 | Pentium III | Coppermine (cD0-step) |
| 80534 | Pentium 4 SFF | Northwood (small form factor) |
| 80535 | Pentium M, Celeron M 310–340 | Banias |
| 80536 | Pentium M, Celeron M 350–390 | Dothan |
| 80537 | Core 2 Duo T5xxx, T7xxx, Celeron M 5xx | Merom |
| 80538 | Core Solo, Celeron M 4xx | Yonah |
| 80539 | Core Duo, Pentium Dual-core T-series | Yonah |
| 80541 | Itanium | Merced |
| 80542 | Itanium 2 | McKinley |
| 80543 | Itanium 2 | Madison |
| 80546 | Pentium 4, Celeron D, Xeon | Prescott (Socket 478), Nocona, Irwindale, Cranford, Potomac |
| 80547 | Pentium 4, Celeron D | Prescott (LGA 775) |
| 80548 | canceled | Tejas and Jayhawk |
| 80549 | Itanium 2 90xx | Montecito |
| 80550 | Dual-core Xeon 71xx | Tulsa |
| 80551 | Pentium D, Pentium EE, Dual-core Xeon | Smithfield, Paxville DP |
| 80552 | Pentium 4, Celeron D | Cedar Mill |
| 80553 | Pentium D, Pentium EE | Presler |
| 80554 | Celeron 800/900/1000 ULV | Shelton |
| 80555 | Dual-core Xeon 50xx | Dempsey |
| 80556 | Dual-core Xeon 51xx | Woodcrest |
| 80557 | Core 2 Duo E4xxx. E6xxx, Dual-core Xeon 30xx, Pentium Dual-core E2xxx | Conroe |
| 80560 | Dual-core Xeon 70xx | Paxville MP |
| 80562 | Core 2 Quad, Core 2 Extreme QX6xxx, Quad-core Xeon 32xx | Kentsfield |
| 80563 | Quad-core Xeon 53xx | Clovertown |
| 80564 | Xeon 7200 | Tigerton-DC |
| 80565 | Xeon 7300 | Tigerton |
| 80566 | Atom Z5xx | Silverthorne |
| 80567 | Itanium 91xx | Montvale |
| 80569 | Core 2 Quad Q9xxx, Core 2 Extreme QX9xxx, Xeon 33xx | Yorkfield |
| 80570 | Core 2 Duo E8xxx, Xeon 31xx | Wolfdale |
| 80571 | Core 2 Duo E7xxx, Pentium Dual-core E5xxx, Pentium Dual-core E2210 | Wolfdale-3M |
| 80573 | Xeon 5200 | Wolfdale-DP |
| 80574 | Core 2 Extreme QX9775, Xeon 5400 | Harpertown |
| 80576 | Core 2 Duo P7xxx, T8xxx, P8xxx, T9xxx, P9xxx, SL9xxx, SP9xxx, Core 2 Extreme X9xxx | Penryn |
| 80577 | Core 2 Duo P7xxx, P8xxx, SU9xxx, T6xxx, T8xxx | Penryn-3M |
| 80578 | EP80578 | Vermilion Range |
| 80579 | EP80579 | Tolapai |
| 80580 | Core 2 Quad Q8xxx, Q9xxx, Xeon 33xx | Yorkfield-6M |
| 80581 | Core 2 Quad Q9xxx | Penryn-QC |
| 80582 | Xeon 74xx | Dunnington |
| 80583 | Xeon 74xx | Dunnington-QC |
| 80584 | Xeon X33x3 LV | Yorkfield CL |
| 80585 | Core 2 Solo SU3xxx, Celeron 7xx, 9xx | Penryn-L |
| 80586 | Atom 2xx, N2xx | Diamondville |
| 80587 | Atom 3xx | Diamondville DC |
| 80588 | Xeon L3014, E3113 | Wolfdale-CL |
ਇੰਟਲ 806xx product codes
ਸੋਧੋ| Product code | Marketing name(s) | Codename(s) |
|---|---|---|
| 80601 | Core i7, Xeon 35xx | Bloomfield |
| 80602 | Xeon 55xx | Gainestown |
| 80603 | Itanium 93xx | Tukwila |
| 80604 | Xeon 65xx, Xeon 75xx | Beckton |
| 80605 | Core i5-7xx, Core i7-8xx, Xeon 34xx | Lynnfield |
| 80606 | canceled | Havendale |
| 80607 | Core i7-7xx QM, Core i7-8xx QM, Core i7-9xx XM | Clarksfield |
| 80608 | canceled | Auburndale |
| 80609 | Atom Z6xx | Lincroft |
| 80610 | Atom N400, D400, D500 | Pineview |
| 80611 | canceled | Larrabee |
| 80612 | Xeon C35xx, Xeon C55xx | Jasper Forest |
| 80613 | Core i7-9xxX, Xeon 36xx | Gulftown |
| 80614 | Xeon 56xx | Westmere-EP |
| 80615 | Xeon E7-28xx, Xeon E7-48xx, Xeon E7-88xx | Westmere-EX |
| 80616 | Pentium G6xxx, Core i3-5xx, Core i5-6xx | Clarkdale |
| 80617 | Core i5-5xx, Core i7-6xxM/UM/LM | Arrandale |
| 80618 | Atom E6x0 | Tunnel Creek |
| 80619 | Core i7-3xxx | Sandy Bridge-EP |
| 80620 | Xeon E5-24xx, Xeon E5-14xx, Pentium 14xx | Sandy Bridge-EN |
| 80621 | Xeon E5-16xx, Xeon E5-26xx, Xeon E5-46xx | Sandy Bridge-EP-8, Sandy Bridge-EP-4 |
| 80622 | Sandy Bridge-EP-8 | |
| 80623 | Xeon E3-xxxx, Core i3/i5/i7-2xxx, Pentium Gxxx, Xeon E3-12xx | Sandy Bridge-HE-4, Sandy Bridge-M-2 |
| 80627 | Core i3/i5/i7-2xxxM, Pentium Bxxx, Celeron Bxxx | Sandy Bridge-HE-4, Sandy Bridge-H-2, Sandy Bridge-M-2 |
| 80631 | Itanium 95xx | Poulson |
| 80632 | Atom E6x5C | Stellarton |
| 80633 | Core i7-48xx, -49xx | Ivy Bridge-E |
| 80634 | Xeon E5-24xx-v2, E5-14xx-v2, Pentium-14xx-v2 | Ivy Bridge-EN |
| 80635 | Xeon E5-26xx-v2, E5-16xx-v2 | Ivy Bridge-EP |
| 80636 | Xeon E7-v2 | Ivy Bridge-EX |
| 80637 | Core i5/i7-3xxx, Xeon-E3 | Ivy Bridge |
| 80638 | Mobile Core i5/i7-3xxxM | Ivy Bridge |
| 80640 | Atom Z24xx | Penwell |
| 80641 | Atom D2xxx, Atom N2xxx | Cedarview |
| 80642 | Atom Z2xxx | Penwell |
| 80644 | Xeon E5-16xx/26xx-v3 | Haswell-EP |
| 80646 | Core i3/i5/i7 - 4xxx, Pentium G3xxx, Celeron G18xx, Xeon E3-12xx-v3 | Haswell |
| 80647 | Core i5/i7 - 4xxxM | Haswell-H, Haswell-M |
| 80648 | Core i7-58xx, -59xx | Haswell-E |
| 80649 | Xeon Phi | Knight's Corner |
| 80650 | Atom Z27xx | Cloverview |
| 80651 | Atom Z25xx | Cloverview |
| 80652 | Atom Z33xx | Merrifield |
| 80653 | Atom Z37xx | Bay Trail-T |
| 80654 | Atom C23xx | Avoton |
| 80655 | Atom C2356 | Rangeley |
| 80658 | Core i3/i5/i7 - 5xxx, Core M - 5Yxx | Broadwell-Y, Broadwell-U, Broadwell-H |
| 80661 | Quark SoC X10xx | Clanton |
| 80662 | Core i3/i5/i7 - 6xxx, Core m3/m5/m7 - 6Yxx, Pentium G4xxx, Xeon v5 | Skylake |
| 80663 | Atom Z35xx | Moorefield |
ਹਵਾਲੇ
ਸੋਧੋ- ↑ The 4004's original goal was to equal the clock rate of the IBM 1620 Model I (1MHz); this was not quite met.
- ↑ http://www.depi.itch.edu.mx/apacheco/asm/ਇੰਟਲ_cpus.htm[permanent dead link]
- ↑ 3.0 3.1 3.2 "ਇੰਟਲ Microprocessor Quick Reference Guide – Product Family". Retrieved 2010-01-08.
{{cite web}}: Check|url=value (help)[permanent dead link] - ↑ 4.0 4.1 4.2 ਇੰਟਲ IAPX 86,88 User's Manual, August 1981, ਇੰਟਲ order number 210201-001
- ↑ ਇੰਟਲ Processor Spec Finder for Celeron M[permanent dead link] ਫਰਮਾ:WebCite
- ↑ Not listed as an official model by ਇੰਟਲ but used by Apple in their ਇੰਟਲ-based Mac Mini, released March 2006 Archived ਸਤੰਬਰ 28, 2014 at the Wayback Machine
- ↑ "ਇੰਟਲ Pentium Processor G6950 (3M Cache, 2.80GHz) with SPEC Code(s) SLBMS". Ark.ਇੰਟਲ.com. 2010-07-13. Archived from the original on 2011-01-22. Retrieved 2010-07-29.
{{cite web}}: Check|url=value (help); Unknown parameter|deadurl=ignored (|url-status=suggested) (help)